For an introduction to Address-Event Representation (AER), see Chapter 3, "The Silicon Optic Nerve" in "An analog VLSI System for Steroscopic Vision" by Misha Mahowald, Kluwer Academic Publishers, 1994, ISBN 0-7923-9444-5. This book was based on Misha's doctoral thesis.
Briefly, Address-Event Representation describes a family of multiplexing protocols developed for communication between analog VLSI (aVLSI) chips bearing spiking neuromorphs in which the event of a neuromorph generating an action potential is represented by a bus-cycle on an unclocked digital bus that carries the address of the neuromorph that was responsible for the event.
The protocol described in Misha's book and used since by other workers in Carver Mead's 'Physics of Computation' group at Caltech and elsewhere is for single sender, single receiver systems. This is known as AER 0.02, or the Point-to-Point (P2P) AER protocol. For the SCX-1 Local Address-Event Bus (LAEB) we wanted to have a protocol that would allow multiple senders and multiple receivers on the same bus.
The following section is a reproduction of a diagram drawn by Steve Deiss of Applied Neurodynamics, after the original rough draft for the protocol (Deiss et al. 1994, Figure 0.2) that emerged from discussions in 1994 involving Steve Deiss, Rodney Douglas, Mike Fischer, Misha Mahowald and Tony Matthews, and later also Tobi Delbrück and Adrian Whatley.
Address-Event Asynchronous Local Broadcast Protocol
SRD, ANdt, 062894 2e
If Arbitration and strobing is centralized and clock driven, the protocol is effectively synchronous although events occur asynchronuosly.
Times given in ns.
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All NN IC inputs TTL threshold. |
The transaction protocol is specified so that either edge of /STROBE can latch the address of the event with 25 ns or more of setup time and 5 ns or more of hold time. NOTE that /WAIT must be implemented as open collector - open drain.
Either the Arbiter drives the /STROBE line or all the NN chips each drive it, but a mixture of the two schemes is not presently allowed on SCX-1 due to FPGA limitations.
Each device connected to the local AE bus has it's own dedicated pair of request (/REQn) and acknowledge (/ACKn) lines. All the other lines of the bus are common to all the devices on the bus.
When a device wishes to transmit an AE on the bus (after any device-local arbitration, eg. on-chip arbiter tree based arbitration between neurons) it makes a request by lowering its /REQn line. When the bus arbiter wishes to let a requesting device transmit, it will drive the corresponding /ACKn line low. Only when the requesting device sees its /ACKn low may it drive the AE data bits onto the lines AE0-15 (all 16 bits should be driven to a definite state). At all other times it must not drive any of these bits. In addition to driving the data onto the data bus in response to the acknowledge signal, the requester should remove its request (/REQn goes high) and not assert it (low) again until /ACKn has gone high. Currently, the /READ (or /STROBE) signal is generated by the arbiter. The transmitting device must adhere to the timing constraints shown in the diagram above and must stop driving the AE0-15 lines when the /ACKn line goes high.
Passive listener devices may exist on the bus that do not generate any request signals. These devices monitor the AE activity on the bus by latching the data bits from AE0-15 on either of the edges of the /READ signal.
The /WAIT and /TIMEOUT signals are designed to implement a mechanism whereby a slow acting device may delay the bus arbiter from continuing with a further bus cycle (by granting an acknowledge to some device) for up to 1 microsecond. To cause such a delay, a device may assert /WAIT (low) after the low going edge of /READ, and de-assert it either when sufficient delay for its purposes has elapsed, or in any event when a low going edge occurs on /TIMEOUT. (/TIMEOUT will be driven low by the bus arbiter if /WAIT is still low 1µs after it is first asserted.) The use of this /WAIT and /TIMEOUT feature is discouraged, and no device has as yet made use of it.
Peripheral AE devices are encouraged to adopt the 26-way IDC pinout described on the 'SCX project - Daughterboards' page as their physical connection standard.
