SCX project - Daughterboards

The SCX board has provision for mounting relatively large daughterboards for expansion purposes, such as

• Adding more MNC sockets to bring the total number of MNCs supported by one SCX-1 board up to the maximum of six.
• Connecting to peripheral sensors and/or effectors.

To date only one type of daughterboard has been designed, Silicon Cortex Daughter Board 1.

Daughterboard connector

Physically the daugterboard connector (J3) is an FCI Micropax 160-position surface mount receptacle, part number 91403-002. This connector was chosen primarily to minimize the amount of board area required.

The pinout on this connector is as follows:

Signals are as follows:

Power:

GND        Unfiltered ground from VME bus backplane.
VCC        Unfiltered +5V supply from VME bus backplane.
-12        Unfiltered -12V supply from VME bus backplane.
+12        Unfiltered +12V supply from VME bus backplane.
PROGV      Programming Voltage (eg. for floating gates) from JP5:
               if a link is fitted across JP5, PROGV = +12.

MUX bus:

MXC0..15   Data, eg. a synapse or parameter address.
/MXCS2..5  Active low chip selects.
               (/MXCS0 & /MXCS1 serve the MNC sockets on the SCX-1 board)
MXL/R      'LOAD' or 'REFRESH' signal:
               low usually indicates data is a synaptic address;
               high usually indicates data is a parameter address.
/DAV       Active low Data Valid signal indicates validity of above signals.
MUXO0..6   Undedicated output lines (from MUX bus devices) readable in HCR.
MNCT0..3   Undedicated MUX bus device control lines, writeable via MUX bus FIFO.

Local Address Event bus (LAEB):

AE0..15    Address Event data
/REQ1..4   Active low Request lines from daughterboard AE devices 1 to 4.
/ACK1..4   Active low Acknowledge lines to daughterboard AE devices 1 to 4.
/READ      LAEB 'Strobe' signal from SCX-1. Low indicates interval in which data may be read.
/WAIT      'Wait' signal.
/TIMEOUT   'Timeout' signal.

For adetailed description of the LAEB signals, refer to the Address-Event protocol page

'C50 address and data buses:

TA0..13    Least significant 14 bits of processor address bus.
BTD0..15   Buffered processor data bus.
/DTCS      Active low daughterboard select signal. Low when daughterboard is being addressed,
               ie. when A14 and A15 are high and low respectively, so that daughterboard
               devices may be memory mapped between addresses 4000-7FFF.
B/ST       Buffered 'C50 /ST strobe signal.
BR/W       Buffered R/W read not write signal.
CK1        Clock signal derived from 'C50's CKOUT1.

Miscellaneous:

DBDD       Daughterboard detect. All daughterboards should drive this line high so that the
               presence of the daughterboard can be detected via the DBDD bit in the HCR.
/DBDI      Daughterboard interrupt. Daughterboard devices may interrupt the 'C50 using this line.
/RESET     Power on and front panel push button reset signal.
RSV1       Reserved.
NC         No connection.

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Silicon Cortex Daughter Board 1

Silicon Cortex Daughter Board 1 was designed by Brian Baker. It primarily serves to bring the Local Address-Event Bus (LAEB) out to two ports towards the front of the SCX-1 board / daughterboard combination to facilitate the attachment of remote AE peripherals. In order to make the ports suitable for peripherals to be attached on the end of moderately long cables, this daughterboard buffers the AE bus data bits, request, acknowledge and read strobe signals. The secondary purpose of this daughterboard is to provide three headers via which a logic analyser may be more easily connected directly to the unbuffered LAE and MUX buses for debugging and/or data collection purposes. This daughterboard is approximately 17cm x 11.5cm.

The LAEB ports consist of standard 0.1 inch pitch 26-way male headers suitable for connection to ribbon-cable mounted IDC connectors. The pinout on these connectors is as follows:

Signal names are as above.

We intend this to become the standard connection for single AE protocol peripherals.

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