The gateway labs developed by Tom Clayton and Kkaled Benkrid at the University of Edinburgh provide a step-by-step introduction to using the verilog HDL (hardware description language) to design synchronous logic using FPGAs.
The exercises are based around the Digilent BASYS2 board which has a Xilinx Spartan 3 FPGA. See fpga for tool setup and resources.
The exercises consist of the following
- Making a new project with a module
and controlling a single LED with a button.
Hello lots of Worlds
- making a bus
to wire all switches to all LEDs; the UCF (User Constraints File).
- using registers
, simulation with a verilog test fixture
; the sensitivity list
in always@ in simulation. “If within a module you have a signal that is on the left hand side of an assignment within an 'always@(…)' statement, then it needs to be defined as a register ('reg')”.
- synthesizing a shift register with fd
D-FlipFlops using gate level and behavioral level design; register transfer level (RTL)
design; module instantiation
; signal concatenation
; introduction to generate
- a second-counter watch using two counters, one clocking the other, both up/down with enable.
- multiple counters, using generics
to instantiate modules with parameters; revisit generate
- making state machines
using sequential and combinational blocks (switch/case statements) and using ROM modules ($readmemb).