Gateway Lab Overview


Aim

To produce students who are capable of developing synchronous digital circuits from high level functional specifications and prototyping them on to FPGA hardware using a standard hardware description language.

Objectives

  1. To explain and illustrate combinatorial and sequential circuits and present a number of ways of designing, and capturing them in a standard hardware description language e.g. Verilog;
  2. To explain and illustrate basic and linked state machines for controlling circuit behaviour, and present a number of ways of designing, and capturing them in standard hardware description language;
  3. To explain and illustrate the notion of modular design and design for reuse, and ways of capturing this in a standard hardware description language;
  4. To present a digital circuit development flow that captures functional specification, design, simulation, synthesis, implementation and testing on FPGA hardware, and illustrate it using a commercial tool suite.

Learning Outcomes

1. Knowledge and understanding of:

I. Combinatorial and sequential circuits and number of ways of designing them;

II. Basic and linked state machines and a number of ways of designing them;

III. The importance of modular design, and design for reuse;

IV. The importance of a structured circuit development flow including functional specification, design, simulation, synthesis, implementation and testing;

V. A standard hardware description language and how it can be used to capture digital circuit designs at different levels of abstraction;

2. Intellectual

I. Ability to use and choose between different techniques for digital circuit design and capture;

II. Ability to evaluate synthesis results and correlate them with the corresponding high level design and capture;

3. Practical

I. Ability to use a commercial digital circuit development tool suite to develop synchronous digital circuits and prototype them on to FPGA hardware;


Teaching and Learning Methods

1. Knowledge and Understanding

I. Short lecture presentations at the start of a number of lab sessions as well as material covered during hands-on lab sessions;

II. Short lecture presentations at the start of a number of lab sessions as well as material covered during hands-on lab sessions;

III. Short lecture presentations at the start of a number of lab sessions as well as material covered during hands-on lab sessions;

IV. Short lecture presentations at the start of a number of lab sessions as well as material covered during hands-on lab sessions;

V. Short lecture presentations at the start of a number of lab sessions as well as material covered during hands-on lab sessions;

2. Intellectual

I. Hands-on lab sessions; highlighted during short lecture presentations at the start of a number of lab sessions;

II. Hands-on lab sessions; highlighted during short lecture presentations at the start of a number of lab sessions;

3. Practical

I. Developed through hands-on lab sessions.


Assessment Methods

1. Knowledge and Understanding

I. Continuous formative assessment during lab sessions with five summative checkpoints, in addition to a final written report;

II. Continuous formative assessment during lab sessions with two summative checkpoints, in addition to a final written report;

III. Continuous formative assessment during lab sessions with five summative checkpoints, in addition to a final written report;

IV. Continuous formative assessment during lab sessions with five summative checkpoints, in addition to a final written report;

V. Continuous formative assessment during lab sessions with five summative checkpoints, in addition to a final written report

2. Intellectual

I. Continuous formative assessment during lab sessions with five summative checkpoints, in addition to a final written report;

II. Continuous formative assessment during lab sessions with five summative checkpoints, in addition to a final written report;

3. Practical

I. Continuous formative assessment during lab sessions with five summative checkpoints, in addition to a final written report;


Labs Timetable and Assessment Deadlines

There are nine weekly scheduled lab sessions starting from Week 2, with the following timetable showing the module(s) to be covered every week with the corresponding assessment points:

Lab 1 - Week 2: "HelloWorld" and "HelloLotsofWorlds" modules

Lab 2 - Week 3: "HelloSynchronousWorld", "ShiftingTheWorld" and "ShiftingManyWorlds" modules

Lab 3 - Week 4: "CountingTheWorld" and "TimingTheWorld" modules

Lab 4 - Week 5: "DecodingTheWorld" module

Lab 5 - Week 6: "TimingTheWorldInDecimalNow" module

Lab 6 - Week 7: "ColouringTheWorld" module

Lab 7 - Week 8: "TheWorldofStateMachines" and "TheWorldofLinkedStateMachine" modules

Lab 8 - Week 9: "Snake" Game module

NB. An extra assessment lab session (Lab 9) will be provided on Week 10 to assess the workings of Lab 8.

The assessment for this lab consists of two components:

1- Continuous assessment during lab sessions with five scheduled checkpoints. These will account for 80% of your overall Gateway lab mark.

2- A final report submission to be handed in electronically through WebCT by Wednesday 08 December 2010 @4:30pm. This will account for the remaining 20% of the overall Gateway lab mark.


Continuous Assessment

The continuous assessment will consist of the following five checkpoints (at each checkpoint, you will be allocated a precise 10mn timeslot to demonstrate your work to your Lead Demonstrator in the lab):

Checkpoint # 1:

By the end of Lab 4 session (Week 5) i.e. after the completion of the "TimingTheWorld" learning module, you should have demonstrated the following to your Lead Demonstrator "live" in the lab:

1) Demonstration of working "TimingTheWorld" module

2) Explanation of Clocks and their importance

3) Explanation of Multiplexing

4) Explanation of Shift Registers

5) Walk through the code explaining what each section does

6) Explain what code re-use is, and why it is important

Checkpoint # 2:

By the end of Lab 6 session (Week 7) i.e. after the completion of the "TimingTheWorldNowInDecimal" learning module, you should have demonstrated the following to your Lead Demonstrator "live" in the lab:

1) Demonstration of working "TimingTheWorldNowInDecimal" module

2) Explanation of Generics

3) Explanation of the 7-Segment Display and the various ways you can write the decoder

4) Walk through the code explaining what each section does, and how it relates to the documentation

Checkpoint # 3:

By the end of Lab 7 session (Week 8) i.e. after the completion of the "ColouringTheWorld" learning module, you should have demonstrated the following to your Lead Demonstrator "live" in the lab:

1) Demonstration of working "ColourTheWorld" module

2) Explanation of the VGA standard

3) Explanation of Parameters

4) Walk through the code explaining what each section does

Checkpoint # 4:

By the end of Lab 8 session (Week 9) i.e. after the completion of the "TheWorldofLinkedStateMachines" learning module, you should have demonstrated the following to your Lead Demonstrator "live" in the lab:

1) Demonstration of working "TheWorldofLinkedStateMachines" module.

a. Extra credit is given for interesting display patterns that were not provided.

2) Explanation of State Machines They must draw the simple state machine diagram and label it.

3) Explanation of Linked State Machines and why they are important

4) Explanation of how they expanded the 3-bit state maze to 3-bits (Draw the state Diagram, including the missing states)

5) Walk through the code explaining what each section does

Checkpoint # 5:

By the end of Lab 9 session (Week 10) i.e. after the completion of the "Snake" learning module, you should have demonstrated the following to your Lead Demonstrator "live" in the lab:

1) Demonstration of working "Snake" module.

a. Extra credit is given for extra functionality e.g. increase speed, snake length

2) Explain Generate Statements

3) Explanation of Pseudo Random Number Generators (PRNG) - LFSR

4) Explanation of code re-use, and which modules could be re-used

5) Walk through the code explaining what each section does, and how it does it


Final Report

You are required to submit a final written report (the only written report you are required to submit in this lab) on the overall "Snake" game design and FPGA implementation. The report should contain the "Snake" game's functional specification, design specification, FPGA implementation, and evaluation. A sample skeleton report can be found here (for a simple adder/subtractor example). The report should not exceed 15 pages including appendices with Arial Font, 1.5 line spacing, and 2-cm top/bottom/left/right margins. Only MS Word or PDF format submissions are expected.

The final report will account for 20% of your overall Gateway lab mark.