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+=====Gateway labs=====
+The gateway labs developed by Tom Clayton and Kkaled Benkrid at the University of Edinburgh provide a step-by-step introduction to using the **[[http://en.wikipedia.org/wiki/Verilog|verilog HDL]]** (hardware description language) to design synchronous logic using FPGAs.
+The exercises are based around the Digilent BASYS2 board which has a Xilinx Spartan 3 FPGA. [[fpga2|See fpga for tool setup and resources]].
+The exercises consist of the following
+=====Introductory videos=====
+  * http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/GenericCoding/commentary_003.avi
+  * http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/podcast1/podcast1.html
+  * http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/podcast2/podcast2.html
+=====Modules=====
+  * [[http://www.ini.uzh.ch/~tobi/~hdlworld/Course%2520Overview%2520-%2520READ%2520ME%2520FIRST.html|course introduction]]
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod1/HTML/wsdindex.html|HelloWorld]] - Making a new project with a //module// and controlling a single LED with a button.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod2/HTML/wsdindex.html|Hello lots of Worlds]] - making a //bus// to wire all switches to all LEDs; the UCF (User Constraints File).
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod3/HTML/wsdindex.html|HelloWorldSynchronous]] - using //registers// and //wires//, simulation with a verilog //test fixture//; the //sensitivity list// in always@ in simulation. "If within a module you have a signal that is on the left hand side of an assignment within an 'always@(...)' statement, then it needs to be defined as a register ('reg')".
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod4/HTML/wsdindex.html|ShiftingTheWorld]] - synthesizing a shift register with //fd// D-FlipFlops using gate level and behavioral level design; //register transfer level (RTL)// design; //module instantiation//;  signal //concatenation//; introduction to //generate//.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod5/HTML/wsdindex.html|ShiftingManyWorlds]] - 2d array of shift registers (memory); simulation exercise.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod6/HTML/wsdindex.html|CountingWorlds]] - simple arithmetic, //multiplexing//.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod7/HTML/wsdindex.html|TimingTheWorld]] - a second-counter watch using two counters, one clocking the other, both up/down with enable.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod8/HTML/wsdindex.html|DecodingTheWorld]] - Number representation; 7-segment display //decoder// ([[http://www.ini.uzh.ch/~tobi/wiki/lib/exe/fetch.php?media=dig:basys2_manual.pdf|see BASYS2 manual]]). See [[7seg]] for the code for this exercise.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod9/HTML/wsdindex.html|TimingTheWorldInDecimel]] - multiple counters, using //generics// to instantiate modules with parameters; revisit //generate//.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod10/HTML/wsdindex.html|ColourTheWorld]] - //parameters// in generics; VGA display control to generate sync signals and RGB colors ([[http://www.ini.uzh.ch/~tobi/wiki/lib/exe/fetch.php?media=dig:basys2_manual.pdf|see BASYS2 manual]]).
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod11/HTML/wsdindex.html|WorldOfStateMachines]] - making //state machines// using sequential and combinational blocks (switch/case statements) and using ROM modules ($readmemb).
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod12/HTML/wsdindex.html|WorldOfLinkedStateMachines]] - multiple state machines linked by a master state machine.
+  - [[http://www.ini.uzh.ch/~tobi/~hdlworld/HDLWorld/Mod13/HTML/wsdindex.html|Snake]] - the snake game. See http://youtu.be/iB3tXDpL9hI for working example from 2012.