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+====== Logic design resources ======
+The FPGA part of the course follows the [[gateway|Gateway Lab exercises]] developed at Univ. of Edinburgh by Khaled Benkrid and Tom Clayton.
+We use the [[http://www.digilentinc.com/Products/Detail.cfm?Prod=BASYS2|BASYS2 FPGA board]] shown below from [[http://www.digilentinc.com/index.cfm|Digilent]] for these exercises; there are many [[http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9|PMOD add-on boards]] to extend the BASYS2 functionality.
+{{dig:basys2.jpg?400px|BASYS2 board}}
+We'll be using [[http://en.wikipedia.org/wiki/Verilog|Verilog]] to configure our FPGAs.
+====Installing Xilinx ISE ====
+**Latest news 7.4.2011: We have a working license server for the full Xilinx ISE Design Suite. Check your email to see how to use this license server.**
+You will need to download the following:
+  - [[http://www.xilinx.com/support/download/index.htm|Xilinx ISE FPGA development tools]]. We will provide the huge installer for[[http://www.xilinx.com/support/download/index.htm|Xilinx ISE WebPACK FPGA development tools]] in the class or from {{dig:xilinx_ise_ds_13.1_o.40d.1.1-2.torrent|this torrent}} because the 5GB download is huge. We use[[http://www.utorrent.com/downloads|utorrent]] for windows torrent downloads.
+  - [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2|Digilent's Adept software for windows or linux]], which downloads the FPGA configuration over USB to the BASYS2 board. \\ You may later want to see also [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN|Digilent Plugin for Xilinx Tools]] which enables programming the BASYS2 directly from Xilinx ISE Impact and [[http://community.em.avnet.com/t5/Spartan-6-LX9-MicroBoard/Digilent-plugin-on-ise-13-1/td-p/2070|this informative forum post]].
+  - You might want to first install [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2|Digilent's Adept software for windows or linux]] because this goes quickly.  Under Windows, the Adept installation may also need to download Microsoft run-time libraries.
+  - For the Xilinx ISE installation, you will need about 15GB of free space (on top of the installer download).
+  - Install **either**  "ISE WebPACK" **or** "ISE Design Suite: System Edition".  If you will register with Xilinx and obtain your own free WebPACK license, install //WebPACK//. If you want to use the class license, then you can install //ISE Design Suite: System Edition// which has more powerful functionality and allows larger devices to be programmed. (It's not clear if we would ever use this additional functionality in the class.)
+  - Choose to "Acquire or manage a license key" (default)
+  - **Install** the "Cable drivers" but not  "WinPCAP for Ethernet hardware co-simulation" (we will be downloading FPGA configuration over USB using Digilent's ADEPT program; at the moment it is not clear if we need the Xilinx cable drivers....)
+  - The installation could take 60 minutes and expand to an astounding additional 12GB of disk space {{ dig:xilinx_size.png?100px|Xilinx ISE installation size}}.
+  - If you installed WebPACK, choose "Get free ISE WebPACK license" for the license option.  If you installed System Edition, then follow instructions sent by email for using our floating license server.
+  - Register with Xilinx to get your free license file "Xilinx.lic". Save it and use "Copy license" in the Xilinx license manager to use the the license.
+=== Linux notes ===
+Simon Corrodi reports:
+I installed:
+  - Adept runtime
+  - Adept Utilities from http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2
+  - Xilinx ISE
+The ISE Project Navigator is hidden at "ISE/bin/lin/ise"
+Because the Floorplaner didn't start, I had to add to the "settings.sh" at toplevel if ISE directory:
+  DISPLAY=:0
+  export DISPLAY
+Found at and some more possible problems: https://help.ubuntu.com/community/XilinxISE
+Adept starts with the command: djtgcfg
+  djtgcfg prog -d Basys2 -i 1 -f "FILE"
+(-i 1 to select the PROM)
+==== Downloads ====
+  * See the [[start#schedule|class schedule]] for the logic design exercises.
+  * The exercises are on separate [[http://www.ini.uzh.ch/~tobi/~hdlworld/wsdindex.html|Gateway labs]] pages.
+  * {{dig:adept_application_user_s_manual.pdf|Adept application user manual}} (from Adept installation folder).
+  * {{dig:spartan3eds312.pdf|Xilinx Spartan 3 datasheet}}.
+  * {{dig:basys2_manual.pdf|BASYS2 user manual}}. Very useful guide to get started with the board.
+  * {{dig:basys2_schematics.pdf|BASYS2 schematics}}.
+  * {{dig:basys2_100_250general.zip|BASYS2 UCF file}}. This **User Constraints File** is useful because you can chop out parts of it to wire up your logic to the BASYS2 board outputs in Xilinx ISE.
+  * The [[http://forums.xilinx.com/|Xilinx forums]] have lots of activity.
+==== FAQ ====
+  * **//How can I program the BASYS2 using the PC connection, rather than loading it onto the PROM?//**\\ You need to generate a programming file with a slightly different startup clock option. See http://www.digilentinc.com/Support/FAQs.cfm under the item "When I am using Export to program an FPGA I receive the error "startup clock for this file is CCLK instead of JTAG-CLK, problems will likely occur." What do I do?"  Then use the top option in Adept to load the resulting bit file directly into the FPGA. It only requires a couple of seconds to load the bit file this way, compared to 30s to reprogram the PROM.
+  * **//Which on-board clock should I use?//**\\  You can use **B8** which is the 50MHz clock source.
+~~DISCUSSION~~