"Learning the secret of flight from a bird was a good deal like learning the secret of magic from a magician. After you know the trick and what to look for, you see things you didn't notice when you did not know exactly what to look for." - Orville Wright in 'Flying Magazine', Dec 1913.
NB. From here on down, italics show where there should have been links to other pages, but those pages don't exist.
Multi-Neuron chips (MNCs)
Prototype board
Miscellaneous
The people most closely involved
<RJD to write this bit?>
Goals
Block diagram
Why use VME to provide infrastructure
Interaction of multiple SCX via domain buses
Options for data logging
Daughterboard, sensors and actuators
Equipment list
Outline of software levels
The SCX-1 board uses the address-event protocol to provide a framework for constructing artificial neuronal systems comprised of many chips. We expect that these systems will include sensors such as retinas and cochleas, and motor effectors, as well as central neuronal processing. These chips are to be supplied by the users of the SCX-1 framework, and need to conform to the standards that are described here.
The framework was devised to solve several fundamental problems encountered in building systems of analog chips that use the address-event protocol:
The SCX-1 framework is designed to be a flexible prototyping system, accommodating chips that may be designed to be incorporated into dedicated hardware systems that are not based on programmable interconnections.
The board layout is illustrated below. There are two 84-pin-grid-array sockets to accommodate custom neuron chips. A daughter-board connector is also provided. Daughterboards are to be fabricated by users. Daughterboards can contain up to four elements that need to talk on the LAEB (e.g. four additional custom neuron chips). Daughterboards (or the daughter board connector) can be used to interface to peripheral sensory devices, such as retinae, or motor drivers that use address-events. In addition, the daughter board can be used to mount receiver chips that transform patterns of address events into images for display on a video monitor.
Communication among all of the chips in this system takes place on three address-event buses (AEB's). The control of the AEB's is mediated by synchronous circuitry on the boards, although requests for control of the bus can happen at any time from the custom neuron chips. The decision to use standard synchronous bus arbitration was motivated by the fact that well understood and debugged methods are available to do it.
Communication among the chips on this board takes place via a local address-event bus (LAEB). The local bus arbiter determines which chip will have control of the LAEB at each cycle. The events on the LAEB are fed to a DSP chip through a bidirectional FIFO. The DSP chip can translate events from the LAEB onto two domain buses (DEAB1 and DEAB2) that make connections between boards. Digital circuitry filters the events that occur on the DEAB's and recognizes events that are relevant to the neurons on its board or which need to be transferred through this board. The filter places the domain events in a bidirectional FIFO so that they can be serviced by the DSP chip. The DSP chip can them place them on the LAEB or transfer them from one domain bus to the other as appropriate. (The DSP chip, therefore, also acts as a source of events on the LAEB.)
The multiplexor bus (MUXB) is an additional interface between the custom neuron chips and the DSP. The DSP transmits destination-encoded events to the custom chips via the MUXB. In addition, the MUXB bus allows the DSP to supply analog parameters on the custom chips via a DAC. The DAC used is the Burr-Brown PCM55, being used in current mode.These parameters can be refreshed periodically. Alternatively, a high-voltage input line and digital control lines are provided for analog chips that use tunneling structures.
The parameters of, and connections between the custom chips are programmable. The digital memory stores a list of connections of the neurons that the DSP must service. Loading a new list reconfigures the artificial neural system. Booting the DSP software and loading the list of connections of the system is performed with an extended DSP development system (XDS) available for PCs and Suns from Texas Instruments. The VME bus can be accessed by any VME bus interface; there are VME bus interfaces for Suns and PCs.
The SCX1 board layout.
(in alphabetical order).
Brian Baker, Department of Experimental Psychology, University of Oxford
Stephen R. Deiss, Applied Neurodynamics
Prof. Rodney J. Douglas, Institute of Neuroinformatics of the University & ETH Zurich
Philipp Häfliger, Microelectronic Systems Group of the Department of Informatics at the University of Oslo, formerly of the Institute of Neuroinformatics of the University & ETH Zurich
Dr. Misha Mahowald, deceased, formerly of the Institute of Neuroinformatics of the University & ETH Zurich
Adrian M. Whatley, Institute of Neuroinformatics of the University & ETH Zurich
Institute of Neuroinformatics home page