3. Strait to Implementation



We are not going to perform a simulation for this design, but rather go strait to implementation. This is partly because we did not include a clear signal in our design so the internal register initial value would be undefined causing the whole simulation to produce undefined results, but also because it is often quicker to simulate designs on real FPGA hardware, a practice called: Hardware In the Loop (HIL). In the latter, simulators transmit data to synthesised hardware running live on an FPGA target board, and subsequently read back simulation results from the board. This is not what we will be doing in this module as inputs and outputs will be tied to a slide switch, push button and LEDs on the board itself, but many FPGA hardware/software vendors do provide software and hardware support for HIL simulation. For the purpose of this module simulation, we will need a UCF, so create one, and tie the slide switch, push button and LEDs to it. Remember to include the following line to stop it throwing errors about using a non-dedicated clock pin.

NET "BUTTON" CLOCK_DEDICATED_ROUTE = TRUE;

Finally, implement your design, create a programming file and upload it to your FPGA using the Adept utility. You should now have a functioning binary counter. Note that you may have problems with switch bouncing as with the previous modules.