7. Behavioural Design 2

The correct implementation

If you synthesise the following design, it will produce exactly the same schematic (both RTL and technology) as the gate level version.

But wait...There's more! Notice that there is a pattern to the assignments, where the preceding cell assigns its value to the next in line. Whenever there is a pattern, it is possible to simplify / condense the description, but to do this a new piece of syntax called concatenation must first be introduced.

The concatenation syntax '{' '}' combines (concatenates) the bits of two or more signals (registers or wires). The objects may be single bit (like the input 'IN') or multiple bit (like the array of registers 'DTypes'). For example, we could with concatenation syntax, combine elements from a wire bus, a register bus, and constants, and it would only take up a single line of code.

The code that describes the following arrangement would look like the following. Note that the bits from register array R have had their order reversed by simply using [0:2] instead of [2:0].

assign Out = { 1'b0 , A[6:7], R[0:2], A[1:3] };

For our shift register we can use concatenation to describe the relationship between the elements of the register (what takes the value of what at the rising edge), as the data transfer can be considered as just a re-ordering of bits.

See how the HDL has combined the input 'IN' with the current values of the register to create the same functionality as the previous designs. Synthesis this code and check out the schematics; again they will have exactly the same structure. To check that this still has the same functionality you can run a simulation or just implement the new design on the BASYS 2 board.