3. Levels of Abstraction



HDL can be used at various levels of abstraction (level of detail). The two levels in which you will use are gate level and behavioural. Ultimately, if properly coded, they will both produce the same behaviour. The difference between all levels of abstraction is how much control you give to the synthesis tool for converting your code into a digital design. There is always a tradeoff between this and the quantity and complexity of your code. At one end of the spectrum there is Behavioural, which requires the least amount of coding, but relinquishes significant amount of control to the synthesis tool, and at the other end there is gate level, which requires the coder to hand craft the design, leaving little left for the synthesis tool to do.

Each of these methods, as well as the area between them on the sliding scale, has uses. Most FPGA design uses behavioural code because it is easy to implement and understand. However, sometimes a specific behaviour is required to be implemented in a certain way, either due to time constraints (the design derived from behavioural HDL is too slow), or space constraints (the device is too small for the resources required by the design). Either way, the synthesis tool would normally implement it in the wrong way, and so a gate level implementation is required. For the majority of this laboratory you will be coding behaviourally.


N.B. The word behavioural here is more precisely referred to as "RTL" or Register Transfer Level description. In it, a circuit's behaviour is defined in terms of the flow of signals between registers and the logical operations performed on those signals. In many instances, the word "behavioural" is reserved to descriptions where just the functionality of the circuit is described, with no reference to clocks or time. The mapping of tasks on hardware and scheduling of tasks is left entirely to the synthesis tool. This is the most rigrous definition, especially from a computer science point of view. Note that in the case of RTL descriptions, at least the scheduling is explicitly described in the code - the mapping too is not entirely left to the synthesis tool. Thus, in the strict definition of behavioural descriptions, RTL is not considered behavioural. That said, you will most certainly read or hear about RTL descriptions referred to as behavioural as the exact mapping on hardware is not specified in the code but rather left to the synthesis tool.