LinkedStateMachine Project Status
Project File: LinkedStateMachine_Lab12.xise Parser Errors: No Errors
Module Name: LinkedStateMachine Implementation State: Programming File Generated
Target Device: xc3s100e-4cp132
  • Errors:
No Errors
Product Version:ISE 13.4
  • Warnings:
2 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 97 1,920 5%  
Number of 4 input LUTs 187 1,920 9%  
Number of occupied Slices 137 960 14%  
    Number of Slices containing only related logic 137 137 100%  
    Number of Slices containing unrelated logic 0 137 0%  
Total Number of 4 input LUTs 238 1,920 12%  
    Number used as logic 187      
    Number used as a route-thru 51      
Number of bonded IOBs 38 83 45%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.08      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Sep 3 01:49:10 200902 Warnings (0 new)1 Info (0 new)
Translation ReportCurrentThu Sep 3 01:49:32 2009000
Map ReportCurrentThu Sep 3 01:49:50 2009002 Infos (0 new)
Place and Route ReportCurrentThu Sep 3 01:50:50 2009004 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Sep 3 01:51:02 2009003 Infos (0 new)
Bitgen ReportCurrentThu Sep 3 01:51:12 2009000
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Synthesis Simulation Model ReportOut of DateWed Sep 2 23:34:00 2009

Date Generated: 06/01/2012 - 12:46:31