LinkedStateMachine Project Status | |||
Project File: | LinkedStateMachine_Lab12.xise | Parser Errors: | No Errors |
Module Name: | LinkedStateMachine | Implementation State: | Programming File Generated |
Target Device: | xc3s100e-4cp132 |
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No Errors |
Product Version: | ISE 14.4 |
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2 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 97 | 1,920 | 5% | ||
Number of 4 input LUTs | 187 | 1,920 | 9% | ||
Number of occupied Slices | 137 | 960 | 14% | ||
Number of Slices containing only related logic | 137 | 137 | 100% | ||
Number of Slices containing unrelated logic | 0 | 137 | 0% | ||
Total Number of 4 input LUTs | 238 | 1,920 | 12% | ||
Number used as logic | 187 | ||||
Number used as a route-thru | 51 | ||||
Number of bonded IOBs | 38 | 83 | 45% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 3.08 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Sep 3 01:49:10 2009 | 0 | 2 Warnings (0 new) | 1 Info (0 new) | |
Translation Report | Current | Thu Sep 3 01:49:32 2009 | 0 | 0 | 0 | |
Map Report | Current | Thu Sep 3 01:49:50 2009 | 0 | 0 | 2 Infos (0 new) | |
Place and Route Report | Current | Thu Sep 3 01:50:50 2009 | 0 | 0 | 4 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Thu Sep 3 01:51:02 2009 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report | Current | Thu Sep 3 01:51:12 2009 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Synthesis Simulation Model Report | Out of Date | Wed Sep 2 23:34:00 2009 |