Table of Contents

Gateway labs

The gateway labs developed by Tom Clayton and Kkaled Benkrid at the University of Edinburgh provide a step-by-step introduction to using the verilog HDL (hardware description language) to design synchronous logic using FPGAs. The exercises are based around the Digilent BASYS2 board which has a Xilinx Spartan 3 FPGA. See fpga for tool setup and resources.

The exercises consist of the following

Introductory videos


  1. HelloWorld - Making a new project with a module and controlling a single LED with a button.
  2. Hello lots of Worlds - making a bus to wire all switches to all LEDs; the UCF (User Constraints File).
  3. HelloWorldSynchronous - using registers and wires, simulation with a verilog test fixture; the sensitivity list in always@ in simulation. “If within a module you have a signal that is on the left hand side of an assignment within an 'always@(…)' statement, then it needs to be defined as a register ('reg')”.
  4. ShiftingTheWorld - synthesizing a shift register with fd D-FlipFlops using gate level and behavioral level design; register transfer level (RTL) design; module instantiation; signal concatenation; introduction to generate.
  5. ShiftingManyWorlds - 2d array of shift registers (memory); simulation exercise.
  6. CountingWorlds - simple arithmetic, multiplexing.
  7. TimingTheWorld - a second-counter watch using two counters, one clocking the other, both up/down with enable.
  8. DecodingTheWorld - Number representation; 7-segment display decoder (see BASYS2 manual). See 7seg for the code for this exercise.
  9. TimingTheWorldInDecimel - multiple counters, using generics to instantiate modules with parameters; revisit generate.
  10. ColourTheWorld - parameters in generics; VGA display control to generate sync signals and RGB colors (see BASYS2 manual).
  11. WorldOfStateMachines - making state machines using sequential and combinational blocks (switch/case statements) and using ROM modules ($readmemb).
  12. WorldOfLinkedStateMachines - multiple state machines linked by a master state machine.
  13. Snake - the snake game. See for working example from 2012. And a general overview of the RTL schematic created by Jeffrey Gehrig: Snake Game RTL block diagram.