A scanner is just a short name for a serial-analog-multiplexer. It is a design frame for serially moving data from a chip to an external display. We use scanners as a diagnostic tool, to observe the behavior of large analog VLSI chips, when the chips have far more nodes than the pins available to us, or when the chip has a topography that maps well onto a display device. The design frames are highly developed and reliable.
The paper tutorially describes mixed digital/analog serial multiplexers (scanners) that we use to visualize the activity of one- and two-dimensional arrays of analog VLSI elements. These scanners range from simple one-dimensional devices designed to scan a one-dimensional array onto an oscilloscope, to complete video scanners with integrated sync and blank computation and on-chip video amplifiers.
This directory also holds several completed chips with scanners. These chips were built in a MOSIS process using either 2um or 3um technology in the late 1980's and early 1990's. They are given in both CIF and Tanner .tdb format. They use scalable design rules so the cells should be pretty easily adaptable to more modern MOSIS submicron and deep submicron rules.
These chips are as follows:
The three chips have been tested and function as expected.
Since the time this paper was written, we have tended to not use current-mode readout as much. We now tend towards voltage-mode readout, meaning the pixel drives a voltage onto the output line instead of a current and this voltage is buffered off the chip. The advantage of voltage mode readout is that switching between columns has much smaller transients because switching two voltages onto a line averages between them instead of summing them (as for currents).
Here are a few figures from the paper:
A one-dimensional scanner. Shows how the bit is automagically reloaded when it falls out of the end by using a wired-OR:
A two-dimensional scanner that requires external logic to load the horizontal and vertical shift registers:
A complete scanner frame with sync and blank generation. The bits are automatically loaded into the H and V scanners and a Johnson counter scans each row several times, in order to generate sufficient lines for a video display:
Mass Sivilotti's single-phase shift register. This shift register is very useful because it doesn't require generating and broadcasting a 2-phase non-overlapping clock. You need to careful to size the pass transistors and power transistors correctly or a slave can drive back to the intended master, killing off your bit. See the paper for more details.
Some of my chips that use scanners
Another group that routinely uses these scanner is the Neuroengineering lab at UPenn. They have evolved the circuits and vary their approach. e.g., they use a 2-phase clock now to avoid the worries about transistor sizing and scaling to large arrays (where the clock edges may get blurred) and do not use automagic wired-OR reload of the bit. Instead, a system reset loads a single bit which recirculates. I have seen in demonstrations that this bit sometimes gets lost, but this approach, if it can be made more stable, has the advantage that it burns a lot less static power and is more deterministic in when the bit is reloaded. For a large array, the automagic reload scheme can sometimes have some jitter in the time it takes to load a new bit, because the wired-OR takes finite time to discover that there is no bit in the shift register.
September 13, 2007