A VLSI AER-based system for implementing WTA relational processors
We will explore the function of coupled graph winner-take-all (WTA) circuits as general relational processors, using VLSI address-event based systems. Initially we will connect two custom VLSI chips comprising cooperative-competitive networks of spiking neurons, that implement soft-WTA mechanisms. The initial system will implement a two node graph, where each node is a WTA chip. The nodes represent a dimension in feature space, and the activity of each neuron in the node encodes the tuning to a specific feature. The relation (constrain) between the two features is represented by the recurrent connectivity between the nodes. The connection matrix between neurons across chips will be implemented using the AER infrastructure.
We will use this hardware to explore context dependent processing in which the interpretation of data by one WTA depends on the relation with the other WTA.
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